1. Technical Field
The present invention relates to a band gap reference voltage generation circuit. More specifically, the present invention relates to a band gap reference voltage generation circuit capable of reducing wake up time during the transition from an idle mode to a normal mode and further capable of removing radio frequency (RF) noise of an output voltage.
2. Description of the Related Art
In a semiconductor integrated circuit, stability of an internal operation voltage is very important to secure the reliability of a semiconductor device. That is, even if an external power source voltage changes, such a change must not exert influence upon the integrated circuit. The devices must perform their unique functions in a stable manner. To this end, a band gap reference voltage generation circuit that always supplies a uniform voltage is necessary.
Recently, in semiconductor integrated circuits, since low voltage supply source circuits have been essentially adopted, a reference voltage generation circuit is necessary. However, the band gap reference voltage generation circuit has unstable factors mainly caused by changes in the temperature or process conditions.
The band gap reference voltage generation circuit generates a uniform range of electric potential in spite of a change in the temperature.
FIG. 1 is a circuit diagram illustrating a conventional band gap reference voltage generating circuit.
Referring to FIG. 1, the conventional band gap reference voltage generation circuit may include several components. First, it may include an operation amplifier 10 for outputting a uniform voltage in accordance with a reference voltage input to an inversion terminal (−) and a non-inversion terminal (+). Second, it may include first PMOS transistor PM1 for outputting a bias current corresponding to an output voltage from the operation amplifier 10 using a power source voltage VDD. Third, it may include reference voltage circuit 20 for supplying the reference voltage to the inversion terminal (−) and the non-inversion terminal (+) of the operation amplifier 10 using bias current. Fourth, it may include a start up circuit 30 for driving the entire circuit during power up. Finally, it may include output terminal NO positioned between first PMOS transistor PM1 and reference voltage circuit 20.
First PMOS transistor PM1 is switched in accordance with the output voltage of operation amplifier 10 and includes a source terminal connected to power source voltage VDD and a drain terminal connected to output terminal NO. First PMOS transistor PM1 supplies the bias current corresponding to the output voltage of operation amplifier 10 to reference voltage circuit 20.
Reference voltage circuit 20 may also include several components including a first resistor R1 and a first bipolar transistor Q1 serially connected between output terminal NO and a base voltage VSS. It may also include second and third resistors R2 and R3 and a second bipolar transistor Q2 serially connected between output terminal NO and base voltage VSS.
A first node N1 between first resistor R1 and first bipolar transistor Q1 is connected to inversion terminal (−) of operation amplifier 10.
A node N2 between second resistor R2 and third resistor R3 is connected to non-inversion terminal (+) of operation amplifier 10.
The base terminals of first and second bipolar transistors Q1 and Q2 are connected to base voltage VSS to be current mirrors.
The emitter terminal of first bipolar transistor Q1 is connected to first node N1 and the collector terminal of first bipolar transistor Q1 is connected to base voltage VSS.
The emitter terminal of second bipolar transistor Q2 is connected to third resistor R3 and the collector terminal of second bipolar transistor Q2 is connected to base voltage VSS.
Reference voltage circuit 20 flows uniform current to base voltage source VSS through first and second bipolar transistors Q1 and Q2, which are connected in the current mirrors by the resistivity of first to third resistors R1, R2, and R3. This provides positive and negative reference voltages to inversion terminal (−) and non-inversion terminal (+) of operation amplifier 10.
Operation amplifier 10 outputs a uniform band voltage Vband in accordance with the reference voltage supplied from first and second nodes N1 and N2 of reference voltage circuit 20.
A second PMOS transistor PM2 is connected to power source voltage VDD in the form of a diode to supply power source voltage VDD to first PMOS transistor PM1.
A start up circuit 30 may include several components. First, it may include a third PMOS transistor PM3 controlled in accordance with a power down signal pwd and connected to power source voltage VDD. Second, start up circuit 30 may include a fourth PMOS transistor PM4 whose gate terminal is connected to the source terminal, which is connected to the drain terminal of third PMOS transistor PM3. Third, start up circuit 30 may include first to third NMOS transistors NM1 to NM3 serially connected to fourth PMOS transistor PM4 in the form of diodes. Fourth, start up circuit 30 may include a fifth PMOS transistor PM5 for outputting the output voltage of operation amplifier 10 in accordance with the gate voltage of first to third NMOS transistors NM1 to NM3. Finally, start up circuit 30 may include a fourth NMOS transistor NM4 controlled in accordance with inversed power down signal pwdb and connected to fifth PMOS transistor PM5 and connected to base voltage VSS.
Start up circuit 30 wakes up operation amplifier 10 during a transition from an idle mode to a normal mode.
The conventional reference voltage generation circuit adds the voltage generated by a proportional to the absolute temperature (PTAT) circuit and the voltage of a base-emitter junction having a negative temperature coefficient to each other to output a stable reference voltage that is not affected by a change in temperature.
Most analog & mixed mode IPs are designed with enough margin to be insensitive to temperature, power source voltage, and a change in manufacturing process. However, when a change in the manufacturing process exceeds process mismatch statistical data provided by a foundry industry, production yield is significantly affected.
FIG. 2 is a simulation graph for the band gap outputs of the conventional band gap reference voltage generation circuit.
As illustrated in FIG. 2, the conventional reference voltage generation circuit outputs a stable reference voltage when the two input transistors in operation amplifier 10 are realized in a process having mismatch A of 0%. However, since the conventional reference voltage generation circuit outputs a reference voltage of about 0.4V when the two input transistors in operation amplifier 10 are realized in a process having mismatch B no less than 0.11%, the conventional reference voltage generation circuit cannot be used as a reference voltage circuit.
To be specific, when start up circuit 30 is in the idle mode, the output of operation amplifier 10 is in a high state. During transition from the idle mode to the normal mode, mismatching in which the input port transistor in operation amplifier 10 is beyond an allowable range is generated due to a change in a process or, when start up circuit 30 does not normally operate, the output voltage of operation amplifier 10 in a band gap is not set or in a high state.
Therefore, in a conventional reference voltage generating circuit, during a transition from the idle mode to the normal mode, due to the low wake up time caused by start up circuit 30, operation amplifier 10 does not have a stable wake up point.